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• 4+ years of experience using layout design and verification tools (e.g., cadence, calibreLVS, calibreDRC)
• Familiarity with CMOS-SOI processes, especially Global Foundries 45RFSOI
• Able to operate efficiently in a Linux environment, knowledge of basic UNIX/Linux commands

Job Description Overview

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal stakeholders to provide updates and resolve issues.

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