THE ROLE:

This role is geared towards developing required stdcell library EDA (Electronic Design Automation) views, importing 3rd Party EDA views and qualifying them to work with the tools defined in AMD’s Synthesis and Place and Route flows. The role also drives local design innovation and improvement of critical standard cells that are contributing the most to best power/performance per area.

KEY RESPONSIBILITIES:

• Design and verify custom standard cells using analog design tools. Perform HSPICE/Spectre simulations for standard cells characterization.

• Design, develop and enhance the verification environment, including test benches for relevant EDA views (schematic/verilog/liberty views are some examples).

• Create, maintain and improve design flows and infrastructure systems.

• Benchmark 3rd party Standard Cell Libraries for performance, power, and area including through Synthesis and Place and Route.

IDEAL CANDIDATE WILL HAVE:

• Required: Strong knowledge of CMOS integrated circuits. Working experience with HSPICE or Spectre and other CAD tools required for schematic/layout design. - 3-4+ years' experience

• Experience with ASIC EDA tools used in synthesis, place and route, simulation, static timing analysis, test insertion, and formal verification.

• Experience with Hardware Description Languages such as Verilog.

• Successful development of verification test benches using ModelSim, VCS or NCSim.

• Proficient in UNIX (Linux) platforms

• A good understanding of UNIX, C, Perl, Tcl, SPICE, JavaScript and SKILL are assets.

ACADEMIC CREDENTIALS:

• BS in Electrical Engineering or equivalent.

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